Why does the package, not the die, decide how big an AI chip can get?

The reticle is a hard ceiling

A lithography stepper prints one rectangle of circuitry at a time. The largest rectangle it can expose in a single shot, the reticle field, is about 26 mm by 33 mm, or roughly 858 mm squared. Logic dies have lived under that ceiling for decades.

The package did not. To wire several dies and HBM stacks together, TSMC CoWoS places them on a single slab of silicon called an interposer, and that slab has to be larger than any die it carries. Once the interposer needs to be bigger than one reticle field, you have to stitch multiple exposures together, and every stitch and every extra die compounds the chance that one defect scraps a five-figure package.

Two ways to wire dies together

The monolithic-interposer approach puts one large silicon sheet under everything, with through-silicon vias carrying signal down to the organic substrate. It gives dense, uniform routing, but you are bonding one big fragile piece, so warpage and defect risk both grow with its area.

The embedded-bridge approach inverts that. Instead of one large interposer, it buries small silicon bridges in the organic substrate only at the seams where two dies need dense coupling, and lets cheaper substrate routing handle the rest. Intel EMIB is the named example, and TSMC CoWoS-L uses the same idea with local silicon-interconnect bridges. Bonding many small pieces is structurally higher-yield than bonding one big piece, which is why the bridge approach scales to larger packages before yield gives way.

What the yield numbers actually say

The tradeoff is visible in the roadmaps. Both camps are racing past the single-reticle ceiling, and both are quoting yields that hold up at multiples of it, which is the real story rather than any single winner.

Source: TSMC CoWoS roadmap and Intel EMIB-T figures, Tom’s Hardware and TrendForce, 2025–2026

Why photonics makes packaging the binding constraint

The case where packaging becomes decisive is co-packaged optics, where the optical engine moves out of a pluggable module and onto the same substrate as the switch ASIC or accelerator. The hard part is not getting light through a waveguide. It is getting a thermally sensitive photonic die to sit next to hot logic, survive repeated thermal cycles, take a fiber attach, and pass reliability qualification, all without dragging package yield down.

That is a packaging problem before it is an optics problem, and it is a different axis from the material constraint the optics deep-dive covers. One axis is whether you can supply the indium phosphide lasers at all. The other is whether you can integrate them onto the package at yield. Both have to clear for co-packaged optics to ship at volume.

The proof point on the bench

Intel has run silicon photonics in-house for roughly two decades, and at OFC 2024 it showed a fully integrated optical compute interconnect chiplet: a photonic die with on-chip lasers co-packaged against an electrical die and a CPU, moving 4 Tbps bidirectionally at about 5 pJ per bit, against roughly 15 pJ per bit for a pluggable transceiver. The integration vehicle was the embedded-bridge packaging line.

It is a demonstration, not a shipping product, and it does not settle who wins the market. What it shows is that the bottleneck the optics story points at, getting the photonic engine onto the package and qualified, is being worked at the packaging layer, and that a credible alternative to the dominant interposer line exists there.

Source: Intel OCI chiplet, OFC 2024 (Intel Newsroom, Tom’s Hardware)

Strategic read

When the binding constraint is packaging, advantage flows to whoever can bond large heterogeneous packages at yield and qualify them for the field. That is a second concentration story stacked on the first: you can route around Nvidia’s design margin by building your own chip, but that chip still needs an advanced-packaging slot, and TSMC CoWoS capacity has run a year or more behind demand.

The opening for an alternative packager is real for the same reason. The embedded-bridge approach has a structural yield advantage as packages grow, and the players who own it do not depend on CoWoS allocation. Whether that converts into share is unproven, but it is the clearest pressure-release valve on the packaging bottleneck, and worth watching as photonics pulls more of the system onto the substrate.