Why lithography is the chokepoint on AI chips
One machine prints every leading-edge AI chip on Earth. Its cost roughly doubles every four years, and the light it uses is running into the limits of physics. Lithography is the spine of the AI compute economy — and the spine is bending.
Lithography is the line item that gates fab cost, fab count, and fab geography. ASML scanner shipments cap leading-edge wafer capacity; rising cost per tool caps how many fabs can ever exist.
A chip is a pattern of dozens of layers
A modern chip is a sandwich of dozens of patterned layers. Each layer starts as a blank wafer coated with photoresist; light projects a pattern onto it through a mask; the exposed pattern is etched, doped, or filled. Repeat for every layer until a chip exists. Building one transistor takes sixty to eighty of these patterning steps in sequence.
The smallest feature the light can resolve sets the smallest feature the chip can have. Shorten the wavelength and you draw smaller transistors. Fail to shorten it and the whole node stalls.
The three knobs: wavelength, numerical aperture, K1
Lithography lives on the Rayleigh criterion: the smallest printable feature is roughly the wavelength of the light, divided by the numerical aperture of the optics that catch it, multiplied by a constant the industry calls K1. Shorten the wavelength, widen the optics, or get cleverer with the mask, and you draw smaller transistors.
For thirty years the industry pulled mostly on the wavelength knob: visible, ultraviolet, deep ultraviolet, finally extreme ultraviolet at 13.5 nm. The industry is now mostly pulling on the optics knob (High-NA EUV), while two startups are betting they can shorten the wavelength again.
Lithography is the economic spine of the fab
Rock's Law, named after early Intel investor Arthur Rock, observes that the cost of a semiconductor fab roughly doubles every four years. Moore's Law says transistors per die double every two. Compounded, that gives the industry its core economics: each generation, the same dollar buys more compute. Lithography is the line item that is now bending that curve the wrong way.
A leading-edge fab today costs $20 to $30 billion before a single wafer ships. Intel's Fab 52 in Arizona reportedly needed about fifteen EUV scanners. At $200 to $400 million each that is $3 to $6 billion in lithography tools alone, on top of clean rooms suspended on pistons (the fab floor has to be immune to earthquakes and even passing traffic), HVAC that holds sub-class-100 air, and a copy-exactly discipline so strict that Intel has reportedly matched the brand of paint between sites. The bill is why so few companies still build leading-edge chips.
Source: Chris Miller, "Chip War"; ASML and Intel disclosures
The three eras
The full arc of lithography breaks into three eras. DUV (deep ultraviolet) is where the industry started in the 1980s and where it still lives below the leading edge: i-line, KrF, ArF, immersion, multi-patterning. EUV (extreme ultraviolet) is what makes 5 nm and below economical, built on a tin-droplet plasma and an ASML monopoly that took two decades and several billion dollars of R&D to enable. Next-gen is the bet that ASML's cost curve is bendable: xLight wants to replace the light source with a free-electron laser; Substrate wants to skip EUV entirely and revive X-ray.
Each deep dive below tells one of those stories end to end.
Why this is the binding constraint on AI compute
When a forecaster projects AI accelerator supply five years out, the binding number is not how many fabs are announced. It is how many EUV scanners ASML can build, who is allocated each one, whether High-NA hits its volume targets on schedule, and whether photon economics shift under everyone's feet. The AI compute supply curve is a derivative of the EUV scanner shipment curve, with a lag.
If the cost curve does bend (xLight, Substrate, or something we have not seen yet), the geography of "who can build a fab" flips. That is the real question hiding inside every chart of accelerator shipments.