What is LPDDR5X, and why is it in a data center?
LPDDR is the low-power DRAM built for phones. NVIDIA put it next to the GPU — over the industry's objections — because in a rack where every watt is rationed, energy per bit beats raw bandwidth.
Host-side system memory in an AI rack is power- and capacity-bound, not bandwidth-bound. LPDDR trades peak speed for far lower energy per bit and high density, which is why the memory feeding modern accelerators is mobile DRAM rather than server DDR.
DRAM tuned for battery life
LPDDR — Low-Power Double Data Rate — is the same DRAM cell as everything else: one transistor, one capacitor, refreshed every few milliseconds. What differs is everything around the cell. The interface runs at low voltage over narrow buses, the chip drops into aggressive sleep states between accesses, and the package is built to stack densely in a phone, not to plug into a server DIMM slot. The whole design optimises for energy per bit and physical density rather than the wide, hot, high-voltage interface of standard DDR5.
The "5X" is the generation. LPDDR5X is the current fast tier, pushing the per-pin transfer rate to roughly 9,600 MT/s — fast enough that, ganged across a wide bus, it delivers real bandwidth while still sipping power. It is the memory in essentially every modern phone and thin laptop, which is exactly why putting it in a data center sounded absurd until it did not.
Why low power wins in a rack
In a phone, low power buys battery life. In a 120 kW NVL72 rack, power and cooling are the binding constraints, so every watt spent moving bits is a watt not spent on the matmul. System memory built from LPDDR uses a fraction of the energy per bit of server DDR, which frees power budget for the GPUs and lets more capacity fit inside the same thermal envelope.
This is the same logic that makes tokens-per-watt the unit metric of inference. Once the datacenter is power-limited rather than chip-limited, the memory that wins is not the fastest one — it is the one that delivers enough bandwidth at the lowest energy cost. For the host memory that feeds the GPU, that is LPDDR.
"For cell phones, not data centers"
NVIDIA designed its Vera CPU around LPDDR, and the memory industry pushed back. As Jensen Huang told analysts in 2026, the reaction was disbelief: the host CPU sits crammed in among a stack of power-hungry GPUs, so it had to be extraordinarily energy efficient — and LPDDR was the only DRAM built for that.
"We went to the memory vendors — guys, listen, we're going to design a CPU, it's going to be crammed in with a whole bunch of GPUs, so it's got to be super super energy efficient. Can we use LPDDR? Everybody goes nuts. They go, 'What? It's for cell phones, not data centers.' And all the other CPU vendors picked on us and told us we were stupid. And now look who's the genius now?"
Source: NVIDIA GTC Taipei 2026 Financial Analyst Q&A
Soldered, then socketed
LPDDR has always been soldered down — that is how it lives in a phone, and how it lived in the first AI hosts: Grace Hopper and Grace Blackwell soldered LPDDR5X onto the substrate around the chip. Compact and fast, but frozen at the foundry.
Vera changes the packaging, not the silicon. The same LPDDR5X now ships on SOCAMM modules — small compression-attached cards that keep near-soldered speeds while staying removable. The distinction worth holding onto: LPDDR is the DRAM; SOCAMM is the slot it now snaps into.
LPDDR vs DDR vs HBM
LPDDR does not compete with HBM; it sits below it. HBM is the GPU's fast working set; LPDDR is the cheap, high-capacity host tier feeding it. All three draw from the same three DRAM vendors and the same fabs, which is why a surge in one tightens the others.
- Server DDR5. The traditional host memory: high voltage, wide buses, replaceable DIMMs. Built for bandwidth and serviceability in a CPU server, not for a power-starved GPU tray.
- LPDDR5X. Lower energy per bit, denser, historically soldered — now the host memory of AI accelerators. Trades peak interface speed for power efficiency and capacity.
- HBM. Stacked on-package beside the GPU, thousands of wires wide, enormous bandwidth — and the most expensive, most supply-constrained memory there is. It holds the GPU's working set.
Strategic read
LPDDR in the data center couples two supply chains that used to be separate. When the host tier of every accelerator becomes mobile DRAM, phone demand and AI demand pull from the same well — and the DRAM allocation question gets one more bidder.
For Pere, the read is that LPDDR is a volume-and-power story, not a margin story. It is commodity DRAM, and now that SOCAMM makes it socketed, it is the memory line item a buyer can right-size — which is exactly what the June 2026 selloff misread. The durable margin in AI memory lives in HBM; LPDDR is how NVIDIA keeps the host side cheap and cool enough to build more racks.